FROM : Jeff Laing
DATE : Wed Dec 01 22:25:14 2004
> > If pkt[MSEQ] is not on a 16-bit boundary, you'll get an exception.
>
> I'd figure it would take a few extra cycles to access across word
> boundaries, but an exception? That's harsh.
I couldn't find a PPC specific reference, but according to:
http://publibn.boulder.ibm.com/doc_link/en_US/a_doc_lib/aixassem/alangref/fi
xed_point.htm#HDRC274171423JEFF
(and I have to say I love the synchronicity of the anchor name :-)
--------------------------------------------------------------------
Fixed-Point Load and Store with Update Instructions
(blah blah blah)
In user programs, load and store with update instructions which access an
unaligned data location will be performed by either the hardware or the
alignment interrupt handler of the underlying operating system. An alignment
interrupt will result in the EA not being in the base GPR.
--------------------------------------------------------------------
There tis. "Alignment interrupt handler". Keep your data accesses aligned
the way the CPU likes or suffer the performance penalty.
DATE : Wed Dec 01 22:25:14 2004
> > If pkt[MSEQ] is not on a 16-bit boundary, you'll get an exception.
>
> I'd figure it would take a few extra cycles to access across word
> boundaries, but an exception? That's harsh.
I couldn't find a PPC specific reference, but according to:
http://publibn.boulder.ibm.com/doc_link/en_US/a_doc_lib/aixassem/alangref/fi
xed_point.htm#HDRC274171423JEFF
(and I have to say I love the synchronicity of the anchor name :-)
--------------------------------------------------------------------
Fixed-Point Load and Store with Update Instructions
(blah blah blah)
In user programs, load and store with update instructions which access an
unaligned data location will be performed by either the hardware or the
alignment interrupt handler of the underlying operating system. An alignment
interrupt will result in the EA not being in the base GPR.
--------------------------------------------------------------------
There tis. "Alignment interrupt handler". Keep your data accesses aligned
the way the CPU likes or suffer the performance penalty.
| Related mails | Author | Date |
|---|---|---|
| John Draper | Dec 1, 05:55 | |
| Jeff Laing | Dec 1, 06:05 | |
| Sherm Pendley | Dec 1, 08:23 | |
| Andrew Farmer | Dec 1, 08:36 | |
| Sherm Pendley | Dec 1, 09:46 | |
| Jeff Laing | Dec 1, 12:13 | |
| Sherm Pendley | Dec 1, 12:43 | |
| Jeff Laing | Dec 1, 22:25 | |
| Sherm Pendley | Dec 2, 00:03 | |
| Jeff Laing | Dec 2, 00:10 |






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